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DATASHEET
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
Description
ICS9FG1201 follows the Intel DB1200G Differential Buffer Specification. This buffer provides 12 output clocks for CPU Host Bus, PCI Express, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups (DIF 9:0) and (DIF 11:10) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410 or CK410B main clock generator, such as the ICS954101 or ICS932S401, drives the ICS9FG1201. ICS9FG1201 can provide outputs up to 400MHz.
ICS9FG1201H
Features/Benefits
* * * * * * * Power up default is all outputs in 1:1 mode DIF_(9:0) can be "gear-shifted" from the input CPU Host Clock DIF_(11:10) can be "gear-shifted" from the input CPU Host Clock Spread spectrum compatible Supports output clock frequencies up to 400 MHz 8 Selectable SMBus addresses SMBus address determines PLL or Bypass mode
Key Specifications
* * * DIF output cycle-to-cycle jitter < 50ps DIF output-to-output skew < 50ps within a group DIF output-to-output skew < 100ns across all outputs
* *
56-pin SSOP/TSSOP package Available in RoHS compliant packaging
Funtional Block Diagram
OE#
SPREAD COMPATIBLE PLL
GEAR SHIFT LOGIC
STOP LOGIC
2 DIF(11:10)
10 OE(9:0)#
CLK_IN CLK_IN#
SPREAD COMPATIBLE PLL
GEAR SHIFT LOGIC
STOP LOGIC
10 DIF(9:0)
HIGH_BW# FS_A_410 VTT_PWRGD#/PD SMB_A0 SMB_A1 SMB_A2_PLLBYP# SMBDAT SMBCLK
CONTROL LOGIC
IREF
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H
10/22/07
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ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
Pin Configuration
HIGH_BW# CLK_IN CLK_IN# SMB_A0 OE0# DIF_0 DIF_0# OE1# DIF_1 DIF_1# VDD GND DIF_2 DIF_2# OE2# DIF_3 DIF_3# OE3# DIF_4 DIF_4# OE4# VDD GND DIF_5 DIF_5# OE5# SMB_A1 SMBDAT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDA GNDA IREF OE10_11# DIF_11 DIF_11# VDD GND DIF_10 DIF_10# FS_A_410 VTT_PWRGD#/PD OE9# DIF_9 DIF_9# OE8# DIF_8 DIF_8# VDD GND DIF_7 DIF_7# OE7# DIF_6 DIF_6# OE6# SMB_A2_PLLBYP# SMBCLK
56-pin SSOP & TSSOP
Functionality Table
DIF_(9:0) Output DIF_(11:10) Output MHz MHz 1 100.00 100.00 1 133.33 133.33 1 166.66 166.66 RESERVED 1 0 200.00 200.00 200.00 0 266.66 266.66 266.66 0 333.33 333.33 333.33 0 400.00 400.00 400.00 1. FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. FS_A_410
1
CLK_IN (CPU FSB) MHz 100.00 133.33 166.66
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H
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ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
Power Groups
Pin Number VDD GND 56 55 11,22,38,50 12,23,37,49 Description Main PLL, Analog DIF clocks
Pin Description
Pin # Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 HIGH_BW# CLK_IN CLK_IN# SMB_A0 OE0# DIF_0 DIF_0# OE1# DIF_1 DIF_1# VDD GND DIF_2 DIF_2# OE2# DIF_3 DIF_3# OE3# DIF_4 DIF_4# OE4# VDD GND DIF_5 DIF_5# OE5# SMB_A1 SMBDAT Type IN IN IN IN IN OUT OUT IN OUT OUT PWR PWR OUT OUT IN OUT OUT IN OUT OUT IN PWR PWR OUT OUT IN IN I/O Pin Description 3.3V input for selecting PLL Band Width 0 = High, 1= Low Input for reference clock. "Complementary" reference clock input. SMBus address bit 0 (LSB) Active low input for enabling DIF pair 0. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 1. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 2. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 3. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 4 1 = tri-state outputs, 0 = enable outputs Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 5. 1 = tri-state outputs, 0 = enable outputs SMBus address bit 1 Data pin of SMBUS circuitry, 5V tolerant
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
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ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
Pin Description (continued)
Pin # Pin Name 29 SMBCLK 30 SMB_A2_PLLBYP# Type IN IN Pin Description Clock pin of SMBUS circuitry, 5V tolerant SMBus address bit 2. When Low, the part operates as a fanout buffer with the PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with the PLL operating. 0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used) Active low input for enabling DIF pair 6. 1 = tri-state outputs, 0 = enable outputs 0.7V differential complement clock output 0.7V differential true clock output Active low input for enabling DIF pair 7. 1 = tri-state outputs, 0 = enable outputs 0.7V differential complement clock output 0.7V differential true clock output Ground pin. Power supply, nominal 3.3V 0.7V differential complement clock output 0.7V differential true clock output Active low input for enabling DIF pair 8. 1 = tri-state outputs, 0 = enable outputs 0.7V differential complement clock output 0.7V differential true clock output Active low input for enabling DIF pair 9. 1 = tri-state outputs, 0 = enable outputs Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 3.3V tolerant low threshold input for CPU frequency selection. This pin requires CK410 FSA. Refer to input electrical characteristics for Vil_FS and Vih_FS threshold values. 0.7V differential complement clock output 0.7V differential true clock output Ground pin. Power supply, nominal 3.3V 0.7V differential complement clock output 0.7V differential true clock output Active low input for enabling output pairs 10 and 11. 1 = tri-state outputs, 0 = enable outputs This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core.
31 32 33 34 35 36 37 38 39 40 41 42 43 44
OE6# DIF_6# DIF_6 OE7# DIF_7# DIF_7 GND VDD DIF_8# DIF_8 OE8# DIF_9# DIF_9 OE9#
IN OUT OUT IN OUT OUT PWR PWR OUT OUT IN OUT OUT IN
45
VTT_PWRGD#/PD
IN
46 47 48 49 50 51 52 53
FS_A_410 DIF_10# DIF_10 GND VDD DIF_11# DIF_11 OE10_11#
IN OUT OUT PWR PWR OUT OUT IN
54 55 56
IREF GNDA VDDA
OUT PWR PWR
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
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ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201 Programmable Gear Ratios
FS_A_410 SMBus Byte 0 Bit 3 Bit 2 Bit 1 Bit 0 Input Output Gear Ratio (m) (n) (n/m) Input (CPU FSB) and Output Frequencies (MHz) 200.0 3 5 12 2 5 8 3 4 6 1 5 4 3 2 3 1 1 2 5 1 3 5 2 3 5 1 6 5 4 3 5 2 0.333 0.400 0.417 0.500 0.600 0.625 0.667 0.750 0.833 1.000 1.200 1.250 1.333 1.500 1.667 2.000 266.7 320.0 333.3 400.0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
66.7 88.9 106.7 111.1 133.3 80.0 106.7 128.0 133.3 160.0 83.3 111.1 133.3 138.9 166.7 100.0 133.3 160.0 166.7 200.0 120.0 160.0 192.0 200.0 240.0 125.0 166.7 200.0 208.3 250.0 133.3 177.8 213.3 222.2 266.7 150.0 200.0 240.0 250.0 300.0 166.7 222.2 266.7 277.8 333.3 200.0 266.7 320.0 333.3 400.0 240.0 320.0 384.0 400.0 NA 250.0 333.3 400.0 NA NA 266.7 355.6 NA NA NA 300.0 400.0 NA NA NA 333.3 NA NA NA NA 400.0 NA NA NA NA CLK IN (CPU FSB) Frequency (MHz) 100 133.33 160 166.67
10000 3 1 0.333 10001 5 2 0.400 NA 53.3 64.0 66.7 10010 12 5 0.417 NA 55.6 66.7 69.4 10011 2 1 0.500 50.0 66.7 80.0 83.3 10100 5 3 0.600 60.0 80.0 96.0 100.0 10101 8 5 0.625 62.5 83.3 100.0 104.2 10110 3 2 0.667 66.7 88.9 106.7 111.1 10111 5 4 0.800 80.0 106.7 128.0 133.3 11000 6 5 0.833 NA 111.1 133.3 138.9 11001 1 1 1.000 100.0 133.3 160.0 166.7 11010 5 6 1.200 120.0 160.0 192.0 200.0 11011 4 5 1.250 125.0 166.7 200.0 208.3 11100 3 4 1.333 133.3 177.8 213.3 222.2 11101 2 3 1.500 150.0 200.0 11110 3 5 1.667 166.7 222.2 266.7 277.8 11111 1 2 2.000 200.0 266.7 320.0 333.3 Note: Lines in BOLD are Power-up defaults for FS_A_410 = 0 and 1 respectively. Shaded areas are shown for reference only and are not necessarily valid operating points
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
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ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
9FG1201 SMBus A ddress M apping when using CK410/CK 410B and DB400/800
SMB_A(2:0) = 000 SMB Adr: D0 9FG1201 (DB1200G) SMB Adr: D2 954101 932S401 (CK410/410B)
PLL BYPASS M ODE SMB_A2_PLLBYP# = 0
SMB_A(2:0) = 001 SMB Adr: D2 9FG1201 (DB1200G)
OR
SMB_A(2:0) = 010 SMB Adr: D4 9FG1201 (DB1200G)
SMB_A(2:0) = 011 SMB Adr: D6 9FG1201 (DB1200G)
SMB_A(2:0) = 100 SMB Adr: D8 9FG1201 (DB1200G)
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
PLL FG MODE SMB_A2_PLLBYP# = 1
SMB_A(2:0) = 101 SMB Adr: DA 9FG1201 (DB1200G)
SMB_A(2:0) = 110 SMB Adr: DC 9FG1201 (DB1200G)
OR
SMB Adr: DC 9DB104/108 (DB400/800)
SMB_A(2:0) = 111 SMB Adr: DE 9FG1201 (DB1200G)
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ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
General SMBus serial interface information for the ICS9FG1201H How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D0 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D0 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D1 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D0(H)* WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D0(H)* WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D1(H)* RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
* Note: See SMBus Address Mapping (page 6), for programming SMBus Read/Write Address
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks ICS9FG1201H 10/22/07
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ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
SMBusTable: Gear Ratio Select Register Pin # Name Control Function Byte 0 Group of 10 gear ratio enable DIF(9:0) Bit 7 DIF(11:10) Group of 2 gear ratio enable Bit 6 Reserved Bit 5 Gear Ratio FS4 (FS_A_410) Bit 4 Gear Ratio FS3 Bit 3 Gear Ratio FS2 Bit 2 Gear Ratio FS1 Bit 1 Gear Ratio FS0 Bit 0 SMBusTable: Output Control Register Byte 1 Pin # Name 35, 36 DIF_7 Bit 7 32, 33 DIF_6 Bit 6 24, 25 DIF_5 Bit 5 19,20 DIF_4 Bit 4 16,17 DIF_3 Bit 3 13,14 DIF_2 Bit 2 9,10 DIF_1 Bit 1 6,7 DIF_0 Bit 0
0 1 Type RW Gear Ratio 1:1 RW Gear Ratio 1:1 RW RW See 9FG1201 RW Programmable Gear RW Ratios Table RW RW
PWD 1 1 1 Latch 1 0 1 1
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
SMBusTable: Output and PLL BW Control Register Byte 2 0 Pin # Name Control Function Type Reserved Bit 7 RW High BW see note PLL_BW# adjust Bit 6 RW Bypass see note BYPASS# test mode / PLL Bit 5 Reserved Bit 4 DIF_11 Output Control RW Hi-Z 51,52 Bit 3 Hi-Z 47,48 DIF_10 Output Control RW Bit 2 DIF_9 Output Control RW Hi-Z 42,43 Bit 1 39,40 DIF_8 Output Control RW Hi-Z Bit 0 Note: Bit 6 is wired OR to the pin 1 input, any 0 selects High BW Note: Bit 5 is wired OR to the pin 30 input, any 0 selects Fanout Bypass mode SMBusTable: Output Enable Readback Register Byte 3 Pin # Name Control Function 34 Readback - OE7# Input Bit 7 31 Readback - OE6# Input Bit 6 26 Readback - OE5# Input Bit 5 21 Readback - OE4# Input Bit 4 18 Readback - OE3# Input Bit 3 15 Readback - OE2# Input Bit 2 8 Readback - OE1# Input Bit 1 5 Readback - OE0# Input Bit 0
1 Low BW PLL Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
Type R R R R R R R R
0 Readback Readback Readback Readback Readback Readback Readback Readback
1
PWD X X X X X X X X
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
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ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
SMBusTable: Output Enable Readback Register Pin # Name Control Function Byte 4 46 Readback - FS_A_410 Bit 7 1 Readback - HIGH_BW# In Bit 6 Readback - SMB_A2_PLLBYP# In 30 Bit 5 Reserved Bit 4 Reserved Bit 3 Readback - OE10_11# Input 53 Bit 2 Readback - OE9# Input 44 Bit 1 41 Readback - OE8# Input Bit 0 SMBusTable: Vendor & Revision ID Register Pin # Name Control Function Byte 5 RID3 Bit 7 RID2 Bit 6 REVISION ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 SMBusTable: DEVICE ID Pin # Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type R R R R R R R R
0 Readback Readback Readback Readback Readback Readback Readback Readback
1
PWD X X X X X X X X
Type R R R R R R R R
0 -
1 -
PWD X X X X 0 0 0 1
Name Control Function Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0
Type RW RW RW RW RW RW RW RW
0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
1
PWD 1 1 0 0 0 0 0 1
SMBusTable: Byte Count Register Byte 7 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0
Type RW RW RW Writing to this register RW configures how many RW bytes will be read back. RW RW RW
Control Function
0 -
1 -
PWD 0 0 0 0 1 0 0 1
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
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ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
SMBusTable: 1:1 PLL Frequency Selection Byte 8 Pin # Name Control Function RESERVED Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 RESERVED Bit 3 Frequency Select C Bit 2 Frequency Select B Bit 1 FS_A_410 Bit 0 SMBusTable: Reserved Register Pin # Name Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: M/N Programming Enable Byte 10 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M/N_EN
Type
0
1
RW RW RW
See 9FG1201H 1:1 PLL Programming Table
PWD 0 0 0 0 0 x 1 Latch
Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
0
1
PWD 0 0 0 0 0 0 0 0
Control Function Type Gear PLL and 1:1 PLL M/N Programming RW Enable RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
0 Disable
1 Enable
PWD 0 X X X X X X X
SMBus Table: Gear PLL Frequency Control Register Byte 11 Pin # Name Control Function RESERVED Bit 7 RESERVED Bit 6 Gear PLL M Div5 Bit 5 Gear PLL M Div4 Bit 4 M Divider Programming Gear PLL M Div3 Bit 3 bits Gear PLL M Div2 Bit 2 Gear PLL M Div1 Bit 1 Gear PLL M Div0 Bit 0
Type
0
1
RW RW RW RW RW RW
See 9FG1201H M/N programming Table
PWD X X X X X X X X
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
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ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
SMBus Table: Gear PLL Frequency Control Register Pin # Name Control Function Byte 12 Gear PLL N Div7 Bit 7 Gear PLL N Div6 Bit 6 Gear PLL N Div5 Bit 5 N Divider Programming Gear PLL N Div4 Bit 4 bits Gear PLL N Div3 Bit 3 Gear PLL N Div2 Bit 2 Gear PLL N Div1 Bit 1 Gear PLL N Div0 Bit 0 SMBusTable: Gear PLL Output Divider Register Pin # Name Control Function Byte 13 RESERVED Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 GoutDiv 3 Bit 3 GoutDiv 2 Bit 2 Gear Output Divider GoutDiv 1 Bit 1 GoutDiv 1 Bit 0 SMBusTable: Reserved Register Byte 14 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBusTable: Reserved Register Pin # Name Byte 15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
0
1
See 9FG1201H M/N programming Table
PWD X X X X X X X X
Type
0
1
RW RW RW RW
See Gear Output Divider Table
PWD 0 0 0 0 X X X X
Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
0
1
PWD 0 0 0 0 0 0 0 0
Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
0
1
PWD 0 0 0 0 0 0 0 0
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
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ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
SMBusTable: Reserved Register Pin # Name Byte 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
0
1
PWD 0 0 0 0 0 0 0 0
SMBus Table: 1:1 PLL Frequency Control Register Pin # Name Control Function Byte 17 RESERVED Bit 7 RESERVED Bit 6 1:1 PLL M Div5 Bit 5 1:1 PLL M Div4 Bit 4 M Divider Programming 1:1 PLL M Div3 Bit 3 bits 1:1 PLL M Div2 Bit 2 1:1 PLL M Div1 Bit 1 1:1 PLL M Div0 Bit 0 SMBus Table: 1:1 PLL Frequency Control Register Pin # Name Control Function Byte 18 1:1 PLL N Div7 Bit 7 1:1 PLL N Div6 Bit 6 1:1 PLL N Div5 Bit 5 N Divider Programming 1:1 PLL N Div4 Bit 4 bits 1:1 PLL N Div3 Bit 3 1:1 PLL N Div2 Bit 2 1:1 PLL N Div1 Bit 1 1:1 PLL N Div0 Bit 0
Type
0
1
RW RW RW RW RW RW
See 9FG1201H M/N programming Table
PWD 0 0 X X X X X X
Type RW RW RW RW RW RW RW RW
0
1
See 9FG1201H M/N programming Table
PWD X X X X X X X X
SMBusTable: 1:1 PLL Output Divider Register Byte 19 Pin # Name Control Function Type RESERVED Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 RW 1outDiv 3 Bit 3 RW 1outDiv 2 Bit 2 1:1 Output Divider RW 1outDiv 1 Bit 1 RW 1outDiv 1 Bit 0
0
1
See 1:1 Output Divider Table
PWD 0 0 0 0 X X X X
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
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ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
SMBusTable: Reserved Register Pin # Name Byte 20 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
0
1
PWD 0 0 0 0 0 0 0 0
SMBusTable: Test Byte Register Test Type Test Function Byte 21 RW ICS ONLY TEST Bit 7 RW ICS ONLY TEST Bit 6 RW ICS ONLY TEST Bit 5 RW ICS ONLY TEST Bit 4 RW ICS ONLY TEST Bit 3 ICS ONLY TEST RW Bit 2 RW ICS ONLY TEST Bit 1 ICS ONLY TEST RW Bit 0 Note: Do NOT write to Bit 21. Erratic device operation will result!
Test Result Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PWD 0 0 0 0 0 0 0 0
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
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ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
Absolute Max
PARAMETER 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection SYMBOL VDD_A VDD_In Ts Tambient Tcase ESD prot CONDITIONS MIN GND - 0.5 GND - 0.5 -65 0 Human Body Model 2000 TYP MAX VDD + 0.5V VDD + 0.5V 150 70 115 UNITS Notes V V C C C V
1 1 1 1 1 1
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Current Powerdown Current Input Frequency Pin Inductance Input Capacitance Clk Stabilization Modulation Frequency Tdrive_PD# Tfall_Pd# Trise_Pd# SMBus Voltage Low-level Output Voltage Current sinking at VOL = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time SYMBOL V IH VIL I IH I IL1 VIH_FS VIL_FS I DD3.3OP I DD3.3PD Fi Lpin CIN COUT TSTAB CONDITIONS 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pullup resistors 3.3 V +/-5%, Applies to FS_A_410 pin 3.3 V +/-5%, Applies to FS_A_410 pin all outputs driven all diff pairs driven all differential pairs tri-stated VDD = 3.3 V Logic Inputs Output pin capacitance From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation DIF output enable after PD# de-assertion PD# fall time of PD# rise time of Maximum input voltage @ I PULLUP MIN 2 V SS - 0.3 -5 -5 0.7 V SS - 0.3 V DD + 0.3 0.35 400 70 12 400 7 6 5 1.8 30 33 300 5 5 5.5 0.4 4 (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 1000 300 TYP MAX V DD + 0.3 0.8 5 UNITS Notes V V uA uA V V mA mA mA MHz nH pF pF ms kHz us ns ns V V mA ns ns 1 1 1 1 1 3 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1
100
VMAX VOL I PULLUP TRI2C TFI2C
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
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ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo
1
CONDITIONS V O = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value.
MIN 3000 660 -150 -300 250
TYP
MAX
UNITS NOTES 1 1,3 mV 1,3 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps ps 1 1 1 1 1,2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 1,4,5 1,4
VHigh VLow Vovs Vuds Vcross(abs ) d-Vcross ppm
850 150 1150 550 140
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle
tr tf d-tr d-tf dt3 tJCYC-CYC
Variation of crossing over all edges see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V
-300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175
300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 7.5400 10.0030 10.0533
700 700 125 125 55 50 50
Jitter, Cycle to cycle tJBYP Notes:
Measurement from differential wavefrom PLL mode, from differential wavefrom Bypass mode as additive jitter
45
1.Guaranteed by design and characterization, not 100% tested in production. 2. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that the input frequency meets CK410B accuracy requirements 3.IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. 4. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. 5. Measured from differential cross-point to differential cross-point 6. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
15
ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
Electrical Characteristics - Skew and Differential Jitter Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% Group CLK_IN, DIF[x:0] CLK_IN, DIF[x:0] DIF[11:10] DIF[9:0] DIF[11:0] PLL Jitter Peaking PLL Jitter Peaking PLL Bandwidth PLL Bandwidth Jitter, Phase NOTES:
1. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. 2. Measured from differential cross-point to differential cross-point 3. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 4. This parameter is deterministic for a given device 5. Measured with scope averaging on to find mean value. 6. t is the period of the input clock 7. See http://www.pcisig.com for complete specs 8. Device driven by 932S401EGLF or equivalent 9. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking. 10. Guaranteed by design and characterization, not 100% tested in production. 11. Measured at 3 db dow n or half pow er point.
Parameter t SPO_PLL t PD_BYP t SKEW_G2 t SKEW_G10 t SKEW_A12 jpeak-hibw jpeak-lobw pllHIBW pllLOBW t jphasePLL
Description Input-to-Output Skew in PLL mode (1:1 only), nominal value @ 25C, 3.3V Input-to-Output Skew in Bypass mode (1:1 only), nominal value @ 25C, 3.3V Output-to-Output Skew Group of 2 (Common to Bypass and PLL mode) Output-to-Output Skew Group of 10 (Common to Bypass and PLL mode) Output-to-Output Skew across all 12 outputs (Common to Bypass and PLL mode - all outputs at same gear) (HIGH_BW# = 0) (HIGH_BW# = 1) (HIGH_BW# = 0) (HIGH_BW# = 1) PCIe Gen 1 phase jitter (1.5 - 22 MHz) FBD phase jitter (11-33 MHz)
Min -500 2.5
Typ
Max 500 4.5 50 50 100
Units ps ns ps ps ps dB dB MHz MHz ps
Notes 1,2,4,5,6, 10 1,2,3,5, 10 1,2,10 1,2,10 1,2,3,10 9,10 9,10 10,11 10,11 1,7,8,10
0 0 2 0.7
2.5 2 4 1.4 108 3
ps rms 1,7,8,10
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
16
ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non-coupled 50 ohm trace. 0.5 max L2 length, Route as non-coupled 50 ohm trace. 0.2 max L3 length, Route as non-coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max
Unit inch inch inch ohm ohm Unit inch inch Unit inch inch
Figure 1 1 1 1 1 Figure 1 1 Figure 2 2
Figure 1 Down device routing.
L1 Rs L1' Rs HSCL Output Buffer
L2 L2' Rt L3' Rt L3
L4 L4'
PCI Ex Board Down Device REF_CLK Input
Figure 1
Figure 2 PCI Express Connector Routing.
L1 L1'
Rs
L2 L2'
L4 L4' Rt L3' Rt L3 PCI Ex Add In Board REF_CLK Input
Rs HSCL Output Buffer
Figure 2
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
17
ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
Alternative termination for LVDS and other common differential signals. Figure 3.
Vdiff Vp-p 0.45 v 0.22v 0.58 0.28 0.80 0.40 0.60 0.3 R1a = R1b = R1 Figure_3. Vcm 1.08 0.6 0.6 1.2 R1 33 33 33 33 R2 150 78.7 78.7 174 R3 100 137 none 140 R4 100 100 100 100 Note
ICS874003i-02 input compatible Standard LVDS
L1 L1'
R1a
L2 L2'
R3
L4 L4'
R4
R1b HSCL Output Buffer
R2a L3'
R2b L3 Down Device REF_CLK Input
R2a = R2b = R2
Cable connected AC coupled application, figure 4
Component R5a,R5b R6a,R6b Cc Vcm Value 8.2K 5% 1K 5% 0.1 uF 0.350 volts Note
3.3 Volts
R5a L4 L4'
Cc Cc
R5b
R6a
R6b PCIe Device REF_CLK Input
Figure_4.
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
18
ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
56-Lead, 300 mil Body, 25 mil, SSOP
N
c
SYMBOL
L
E1 INDEX AREA
E
12 h x 45 D
A A1
A A1 b c D E E1 e h L N VARIATIONS N 56
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
D mm. MIN 18.31 MAX 18.55 MIN .720
D (inch) MAX .730
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS 9FG1201HFLF-T
Example:
ICS XXXX H F - LF T
Designation for tape and reel packaging RoHS Compliant Package Type F = SSOP Revision Designator Device Type (consists of 3 to 7 digit numbers)
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
19
ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 56
10-0039
-Ce
b SEATING PLANE
aaa C
D mm. MIN MAX 13.90 14.10
D (inch) MIN .547 MAX .555
Ref erence Doc.: JEDEC Publicat ion 95, M O-153
Ordering Information
ICS 9FG1201HGLF-T
Example:
ICS XXXX H G - LF T
Designation for tape and reel packaging RoHS Compliant Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
20
ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
Revision History
Rev. A Issue Date 10/22/07 Description Release to Final. Page # -
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TM
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA
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